SPIM S20: A MIPS R2000 Simulator
I [am] grateful to the many students at UW who used SPIM in their courses
and happily found bugs in a professor's code. In particular, the students
in CS536, Spring 1990, painfully found the last few bugs in an ``already-
debugged'' simulator. I am grateful for their patience and persistence.
Alan Yuen-wui Siow wrote the X-window interface.
"1/25th the performance at none of the cost"




James R. Larus
larus@cs.wisc.edu
Computer Sciences Department
University of Wisconsin--Madison
1210 West Dayton Street
Madison, WI 53706, USA
608-262-9519
Copyright 1990, 1991 by James R. Larus
Dec. 23, 1991
(Revision 9 corresponding to SPIM Version 4.4)





1 Introduction

SPIM S20 is a simulator that runs programs for the MIPS R2000/R3000 RISC computers. SPIM can read and immediately execute files containing assembly language or MIPS executable files. SPIM is a self-contained system for running these programs and contains a debugger and interface to a few operating system services.

For a description of the real machines, see Gerry Kane, MIPS RISC Architecture, Prentice Hall, 1989.

The architecture of the MIPS computers is simple and regular, which makes it easy to learn and understand. The processor contains 32 general-purpose registers and a well-designed instruction set that make it a propitious target for generating code in a compiler.
However, the obvious question is: why use a simulator when many people have workstations that contain a hardware, and hence significantly faster, implementation of this computer? One reason is that these workstations are not available to most undergraduates since they are used for research. Another reason is that these machine will not persist for many years because of the rapid progress leading to new and faster computers. Unfortunately, the trend is to make computers faster by executing several instructions concurrently, which makes their architecture more difficult to understand and program. The MIPS architecture may be the epitome of a simple, clean RISC machine.
In addition, simulators can provide a better environment for low-level programming than an actual machine because they can detect more errors and provide more features than an actual computer.
For example, SPIM has an X-window interface that is ahead of the debuggers for the actual machines.

Finally, simulators are a useful tool for studying computers and the programs that run on them. Because they are implemented in software, not silicon, they can be easily modified to add new instructions, build new systems such as multiprocessors, or simply to collect data.

2 Simulation of a Virtual Machine

The MIPS architecture, like that of most RISC computers, is difficult to program directly because of its delayed branches and loads and restricted address modes. This difficulty is tolerable since these computers were designed to be programmed in high-level languages and so present an interface designed for compilers, not programmers. A delayed branch takes two cycles to execute. In the second cycle, the instruction immediately following the branch executes. This instruction can perform useful work that normally would have been done before the branch or it can be a nop (no operation). Similarly, delayed loads take two cycles so the instruction immediately following a load cannot use the value from memory.

MIPS wisely chose to hide this complexity by implementing a virtual machine with their assembler. This virtual computer appears to have non-delayed branches and loads and a richer instruction set than the actual hardware. The assembler reorganizes (rearranges) instructions to fill the delay slots. It also simulates the additional, or pseudo, instructions by generating short sequences of actual instructions.

By default, SPIM simulates the richer, virtual machine. It can also simulate the actual hardware. We will describe the virtual machine and only mention in passing features that do not belong to the actual hardware. In doing so, we are following the convention of MIPS assembly language programmers (and compilers), who routinely take advantage of the extended machine. Instructions marked with a dagger (†) are pseudo instructions.

3 SPIM Interface

SPIM provides both a simple terminal and a X-window interface. Both provide equivalent functionality, but the X interface is superior.

spim, the terminal version, and xspim, the X version, have the following command-line options:

-bare
Simulate a bare MIPS machine without pseudo instructions or the additional addressing modes provided by the assembler. Implies -quiet.

-asm
Simulate the virtual MIPS machine provided by the assembler. This is the default.

-notrap
Do not load the standard trap handler. This trap handler has two functions that must be assumed by the user's program. First, it handles traps. When a trap occurs, SPIM jumps to location 0x80000080, which should contain code to service the exception. Second, this file contains startup code that invokes the routine main. Without the trap handler, execution begins at the instruction labeled __start.

-trap
Load the standard trap handler. This is the default.

-noquiet
Print a message when an exception occurs. This is the default.

-quiet
Do not print a message at an exception.

-file
Load and execute the assembly code in the file.

-execute
Load and execute the code in the MIPS executable file a.out. The program cannot invoke any operating system services (e.g., input or output) since SPIM does not simulate the MIPS kernel traps.

-sseg size
Sets the initial size of memory segment seg to be size bytes. The memory segments are named: text, data, stack, ktext, and kdata. For example, the pair of arguments -sdata 2000000 starts the user data segment at 2,000,000 bytes.

-lseg size
Sets the limit on how large memory segment seg can grow to be size bytes. The memory segments that can grow are: data, stack, and kdata.

3.1 Terminal Interface

The terminal interface (spim) provides the following commands:

exit
Exit the simulator.

read "file"
Read file of assembly language commands into SPIM's memory. If the file has already been read into SPIM, the system should be cleared (see reinitialize, below) or global symbols will be multiply defined.

load "file"
Synonym for read.

execute "a.out"
Read the MIPS a.out executable file into SPIM's memory.

run <addr>
Start running a program. If the optional address is provided, the program starts at that address. Otherwise, the program starts at the global symbol __start, which is defined by the default trap handler to call the routine at the global symbol main with the usual MIPS calling convention.

step <N>
Step the program for N (default: 1) instructions. Print instructions as they execute.

continue
Continue program execution without stepping.

print $N
Print register N.

print $fN
Print floating point register N.

print addr
Print the contents of memory at address ADDR.

print_sym
Print the contents of the symbol table, i.e., the addresses of the global (but not local) symbols.

reinitialize
Clear the memory and registers.

breakpoint addr
Set a breakpoint at address ADDR. ADDR can be either a memory address or symbolic label.

delete addr
Delete all breakpoints at address ADDR.

list
List all breakpoints.

.
Rest of line is an assembly instruction that is stored in memory.

<nl>
A newline reexecutes previous command. ?
Print a help message.

Most commands can be abbreviated to their unique prefix e.g., ex, re, l, ru, s, p. More dangerous commands, such as reinitialize, require a longer prefix.

3.2 X-Window Interface

The X version of SPIM, xspim, looks different, but should function the same as spim. The X window has five panes. The top pane displays the contents of the registers. It is continually updated, except while a program is running.

The next pane contains the buttons that control the simulator:

quit
Exit from the simulator.

load
Read a source or executable file into memory.

run
Start the program running.

step
Single-step through a program.

clear
Reinitialize registers or memory.

set value
Set the value in a register or memory location.

print
Print the value in a register or memory location.

breakpoint
Set or delete a breakpoint or list all breakpoints.

help
Print a help message.

terminals
Raise or hide terminal windows.

mode
Set SPIM operating modes.

The next two panes display the memory contents. The top one shows instructions from the user and kernel text segments. (These instructions are real---not pseudo---MIPS instructions. SPIM translates assembler pseudo instructions to 1--3 MIPS instructions before storing the program in memory. Although the instructions in memory look different from the source program, the translation is straight-forward and can be understood with a bit of practice.) The first few instructions in the text segment are startup code (__start) that loads argc and argv into registers and invokes the main routine.

The lower of these two panes displays the data and stack segments. Both panes are updated as a program executes.

The bottom pane is used to display messages from the simulator. It does not display output from an executing program. When a program reads or writes, its IO appears in a separate window, called the Console, which pops up when needed.

4 Surprising Features

Although SPIM faithfully simulates the MIPS computer, it is a simulator and certain things are not identical to the actual computer. The most obvious differences are that instruction timing and the memory systems are not identical. SPIM does not simulate caches or memory latency, nor does it accurate reflect the delays for floating point operations or multiplies and divides.

Another surprise (which occurs on the real machine as well) is that a pseudo instruction expands into several machine instructions. When single-stepping or examining memory, the instructions that you see are slightly different from the source program. The correspondence between the two sets of instructions is fairly simple since SPIM does not reorganize the instructions to fill delay slots (which it only simulates in bare mode).

Comments in assembler files begin with a sharp-sign (#). Everything from the sharp-sign to the end of the line is ignored.

Identifiers are a sequence of alphanumeric characters, underbars (_), and dots (.) that do not begin with a number. Opcodes for instructions are reserved words that are not valid identifiers. Labels are declared by putting them at the beginning of a line followed by a colon, for example:

        .data
  item: .word 1
        .text
        .globl main             # Must be global
  main: lw $t0, item
Strings are enclosed in double-quotes ("). Special characters in strings follow the C convention:
    newline        \n
    tab            \t
    quote          \"
SPIM supports a subset of the assembler directives provided by the MIPS assembler:

.align n
Align the next datum on a 2n byte boundary. For example, .align 2 aligns the next value on a word boundary. .align 0 turns off automatic alignment of .half, .word, .float, and .double directives until the next .data or .kdata directive.

.ascii str
Store the string in memory, but do not null-terminate it.

.asciiz str
Store the string in memory and null-terminate it.

.byte b1, ..., bn
Store the n values in successive bytes of memory.

.data
The following data items should be stored in the data segment.

.double d1, ..., dn
Store the n floating point double precision numbers in successive memory locations.

.extern sym size
Declare that the datum stored at sym is size bytes large and is a global symbol. This directive enables the assembler to store the datum in a portion of the data segment that is efficiently accessed via register $gp.

.float f1, ..., fn
Store the n floating point single precision numbers in successive memory locations.

.globl sym
Declare that symbol sym is global and can be referenced from other files.

.half h1, ..., hn
Store the n 16-bit quantities in successive memory halfwords.

.kdata
The following data items should be stored in the kernel data segment.

.ktext
The next items are put in the kernel text segment. In SPIM, these items must be instructions or words (see the .word directive below).

.space n
Allocate n bytes of space in the current segment (which must be the data segment in SPIM).

.text
The next items are put in the user text segment. In SPIM, these items must be instructions or words (see the .word directive below).

.word w1, ..., wn
Store the n 32-bit quantities in successive memory words.

SPIM does not distinguish various parts of the data segment (.data, .rdata, and .sdata).

6 System Calls

Service		Code	Arguments		Result
print_int	1	$a0 = integer
print_float	2	$f12 = float
print_double	3	$f12 = double
print_string	4	$a0 = string
read_int	5				integer
read_float	6				float
read_double	7				double
read_string	8	$a0 = buffer, $a1 = length
sbrk		9	$a0 = amount		address
exit		10

		Table 1: System services
SPIM provides a small set of operating-system-like services through the system call (syscall) instruction. To request a service, a program loads the type code (see Table 1) into register $v0 and the arguments into registers $a0...$a3 (or $f12 for floating point values). (In earlier versions of SPIM (before 4.0), the type code was passed in register $a0 and the values were slightly different. Programs written for the older versions of SPIM need to be modified to reflect these changes.) System calls that return values put their result in register $v0 (or $f0 for floating point results).

For example, to print ``the answer = 5'', use the commands:

        .data
  str:  .asciiz "the answer = "
        .text
        li $v0, 4        # print_str
        la $a0, str
        syscall
        li $v0, 1        # print_int
        li $a0, 5
        syscall
print_int is passed and integer and prints it on the console. print_float prints a single floating point number. print_double prints a double precision number. print_string is passed a pointer to a null-terminated string, which it writes to the console.

read_int, read_float, and read_double read an entire line of input up to and including the newline. Characters following the number are ignored. read_string has the same semantics as the Unix library routine fgets. It reads upto n-1 characters in a buffer and terminates the string with a null byte. If there are fewer characters on the current line, it reads through the newline and again null-terminates the string.
sbrk returns a pointer to a block of memory containing n additional bytes. exit stops a program from running.

7 Description of the Machine

A MIPS processor consists of an integer processing unit (the CPU) and a collection of coprocessors that perform ancillary tasks or operate on other types of data such as floating point numbers. SPIM simulates two coprocessors. Coprocessor 0 handles traps, exceptions, and the virtual memory system. SPIM simulates most of the first two and entirely omits details of the memory system. Coprocessor 1 is the floating point unit.
SPIM simulates most aspects of this unit.

7.1 CPU Registers

Register Name	Number	Usage
zero		0		Constant 0
at		1		Reserved for assembler
v0		2		Expression evaluation and
v1		3		    results of a function
a0		4		Argument 1
a1		5		Argument 2
a2		6		Argument 3
a3		7		Argument 4
t0		8		Temporary (not preserved across call)
t1		9		Temporary (not preserved across call)
t2		10		Temporary (not preserved across call)
t3		11		Temporary (not preserved across call)
t4		12		Temporary (not preserved across call)
t5		13		Temporary (not preserved across call)
t6		14		Temporary (not preserved across call)
t7		15		Temporary (not preserved across call)
s0		16		Saved temporary (preserved across call)
s1		17		Saved temporary (preserved across call)
s2		18		Saved temporary (preserved across call)
s3		19		Saved temporary (preserved across call)
s4		20		Saved temporary (preserved across call)
s5		21		Saved temporary (preserved across call)
s6		22		Saved temporary (preserved across call)
s7		23		Saved temporary (preserved across call)
t8		24		Temporary (not preserved across call)
t9		25		Temporary (not preserved across call)
k0		26		Reserved for OS kernel
k1		27		Reserved for OS kernel
gp		28		Pointer to global area
sp		29		Stack pointer
fp		30		Frame pointer
ra		31		Return address (used by function call)

Table 2: MIPS registers and the convention governing their use.
The MIPS (and SPIM) central processing unit contains 32 general purpose registers that are numbered 0--31. Register n is designated by $n. Register $0 always contains the hardwired value 0. MIPS has established a set of conventions how the registers should be used. These suggestions are guidelines, which are not enforced by the hardware. However a program that violates them will not work properly with other software. Table 2 lists the registers and describes their intended use.

Registers $at (1), $k0 (26), and $k1 (27) are reserved for use by the assembler and operating system.

Registers $a0--$a3 (4--7) are used to pass the first four arguments to routines (remaining arguments are passed on the stack). Registers $v0 and $v1 (2, 3) are used to return values from functions. Registers $t0--$t9 (8--15, 24, 25) are caller-saved registers used for temporary quantities that do not need to be preserved across calls. Registers $s0--$s7 (16--23) are callee-saved registers that hold long-lived values that should be preserved across calls.

Register $sp (29) is the stack pointer, which points to the first free location on the stack. Register $fp (30) is the frame pointer. (The MIPS compiler does not use a frame pointer, so this register is used as callee-saved register $s8.) Register $ra (31) is written with the return address for a call by the jal instruction.

Register $gp (28) is a global pointer that points into the middle of a 64K block of memory in the heap that holds constants and global variables. The objects in this heap can be quickly accessed with a single load or store instruction.

In addition, coprocessor 0 contains registers that are used for exception handling. SPIM does not implement all of these registers, since they are not of much use in a simulator (or are part of the memory system). However, it does provide the following:

Register Name	Number	Usage
BadVAddr	8		Memory address at which address exception occurred
Status		12		Contains interrupt enable bits
Cause		13		Type of exception
EPC		14		Address of instruction that caused exception
These registers are part of coprocessor 0's register set and can be accessed by the lwc0, mfc0, mtc0, and swc0 instructions.

7.2 Byte Order

Processors can number the bytes within a word to make the byte with the lowest numer either the leftmost or rightmost one. The convention used by a machine is its byte order. MIPS processors can operate with either big-endian byte order:

Byte #
0	1	2	3
or little-endian byte order:
	
Byte #
3	2	1	0
SPIM also operates with both byte orders. SPIM's byte order is determined by the byte order of the underlying hardware that is running the simulator. On a DECstation 3100, SPIM is little-endian, while on a HP Bobcat, Sun 4 or PC/RT, SPIM is big-endian.

7.3 Addressing Modes

MIPS is a load/store architecture, which means that only load and store instructions access memory. Computation instructions operate only on values in registers. The bare machine provides only one memory addressing mode: c(rx), which uses the sum of the immediate (integer) c and the contents of register rx as the address. The virtual machine provides the following addressing modes for load and store instructions:

Format	Address		Computation
(register)			contents of register
imm				immediate
imm (register)			immediate + contents of register
symbol				address of symbol
symbol +/- imm			address of symbol + immediate
symbol +/- imm (register)	address of symbol + (immediate + contents of register)
Most load and store instructions operate only on aligned data. A quantity is aligned if its memory address is a multiple of its size in bytes. Therefore, a halfword object must be stored at even addresses and a full word object must be stored at addresses that are a multiple of 4. However, MIPS provides someinstructions for manipulating unaligned data.

7.4 Load and Store Instructions

la Rdest, address			Load Address†
Load computed address, not the contents of the location, into register Rdest.

lb Rdest, address			Load Byte
lbu Rdest, address			Load Unsigned Byte
Load the byte at address into register Rdest (and sign-extend it).

ld Rdest, address			Load Double-Word†
Load the 64-bit quantity at address into registers Rdest and Rdest + 1.

lh Rdest, address			Load Halfword
lhu Rdest, addressLoad 		Unsigned Halfword
Load the 16-bit quantity (halfword) at address into register Rdest (and sign-extend it).

lw Rdest, address			Load Word
Load the 32-bit quantity (word) at address into register Rdest.

lwcz Rdest, address		Load Word Coprocessor
Load the word at address into register Rdest of coprocessor z (0--3).

lwl Rdest, address			Load Word Left
lwr Rdest, address			Load Word Right
Load the left (right) bytes from the word at the possibly-unaligned address into register Rdest.

sb Rsource, address		Store Byte
Store the low byte from register Rsource at address.

sd Rsource, address		Store Double-Word†
Store the 64-bit quantity in registers Rsource and Rsource + 1 at address.

sh Rsource, address		Store Halfword
Store the low halfword from register Rsource at address.

sw Rsource, address		Store Word
Store the word from register Rsource at address.

swcz Rsource, address		Store Word Coprocessor
Store the word from register Rsource of coprocessor z at address.

swl Rsource, address		Store Word Left
swr Rsource, address		Store Word Right
Store the left (right) bytes from register Rsource at the possibly-unaligned address.

ulh Rdest, address			Unaligned Load Halfword†
ulhu Rdest, address		Unaligned Load Halfword Unsigned
Load the 16-bit quantity (halfword) at the possibly-unaligned address into register Rdest (and sign-extend it).

ulw Rdest, address		Unaligned Load Word†
Load the 32-bit quantity (word) at the possibly-unaligned address into register Rdest.

ush Rsource, address			Unaligned Store Halfword†
Store the low halfword from register Rsource at the possibly-unaligned address.

usw Rsource, address			Unaligned Store Word†
Store the word from register Rsource at the possibly-unaligned address.

7.5 Exception and Trap Instructions

rfe			Return From Exception
Restore the Status register.

syscall			System Call
Register $v0 contains the number of the system call (see Table~\reftab:syscall) provided by SPIM.

break 			nBreak
Cause exception n. Exception 1 is reserved for the debugger.

nop			No operation
Do nothing.

7.6 Constant-Manipulating Instructions

li Rdest, imm		Load Immediate†
Move the immediate into register Rdest.

li.d FRdest, float		Load Immediate Double†
Move the double-precision floating point number into floating point registers FRdest and FRdest + 1.

li.s FRdest, float		Load Immediate Single†
Move the single-precision floating point number into floating point register FRdest.

lui Rdest, integer		Load Upper Immediate
Load the lower halfword of the integer into the upper halfword of register Rdest. The lower bits of the register are set to 0.

7.7 Arithmetic and Logical Instructions

In all instructions below, Src2 can either be a register or an immediate value (integer). The immediate forms of the instructions are only included for reference. The assembler will translate the more general form of an instruction (e.g., add) into the immediate form (e.g., addi) if the second argument is constant.

abs Rdest, Rsource		Absolute Value†
Put the absolute value of the integer from register Rsource in register Rdest.

add Rdest, Rsrc1, Src2		Addition (with overflow)
addi Rdest, Rsrc1, Imm		Addition Immediate (with overflow)
addu Rdest, Rsrc1, Src2		Addition (without overflow)
addiu Rdest, Rsrc1, Imm		Addition Immediate (without overflow)
Put the sum of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.

and Rdest, Rsrc1, Src2		AND
andi Rdest, Rsrc1, Imm		AND Immediate
Put the logical AND of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.

div Rsrc1, RSrc2			Divide (with overflow)
divu Rsrc1, RSrc2			Divide (without overflow)
Divide the contents of the two registers. Leave the quotient in register LO and the remainder in register HI. Note that if an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the conventions of the machine on which SPIM is run.

div Rdest, Rsrc1, Src2		Divide (with overflow)†
divu Rdest, Rsrc1, Src2		Divide (without overflow)†
Put the quotient of the integers from register Rsrc1 and Src2 into register Rdest.

mul Rdest, Rsrc1, Src2		Multiply (without overflow)†
mulo Rdest, Rsrc1, Src2		Multiply (with overflow)†
mulou Rdest, Rsrc1, Src2	Unsigned Multiply (with overflow)†
Put the product of the integers from register Rsrc1 and Src2 into register Rdest.

mult Rsrc1, RSrc2			Multiply
multu Rsrc1, RSrc2		Unsigned Multiply
Multiply the contents of the two registers. Leave the low-order word of the product in register LO and the high-word in register HI.

neg Rdest, Rsource			Negate Value (with overflow)†
negu Rdest, Rsource		Negate Value (without overflow)†
Put the negative of the integer from register Rsource into register Rdest.

nor Rdest, Rsrc1, Src2		NOR
Put the logical NOR of the integers from register Rsrc1 and Src2 into register Rdest.

not Rdest, Rsource		NOT†
Put the logical negation of the integer from register Rsource into register Rdest.

or Rdest, Rsrc1, Src2		OR
ori Rdest, Rsrc1, Imm		OR Immediate
Put the logical OR of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.

rem Rdest, Rsrc1, Src2		Remainder†
remu Rdest, Rsrc1, Src2		Unsigned Remainder†
Put the remainder from dividing the integer in register Rsrc1 by the integer in Src2 into register Rdest. Note that if an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the conventions of the machine on which SPIM is run.

rol Rdest, Rsrc1, Src2		Rotate Left†
ror Rdest, Rsrc1, Src2		Rotate Right†
Rotate the contents of register Rsrc1 left (right) by the distance indicated by Src2 and put the result in register Rdest.

sll Rdest, Rsrc1, Src2		Shift Left Logical
sllv Rdest, Rsrc1, Rsrc2	Shift Left Logical Variable
sra Rdest, Rsrc1, Src2		Shift Right Arithmetic
srav Rdest, Rsrc1, Rsrc2	Shift Right Arithmetic Variable
srl Rdest, Rsrc1, Src2		Shift Right Logical
srlv Rdest, Rsrc1, Rsrc2	Shift Right Logical Variable
Shift the contents of register Rsrc1 left (right) by the distance indicated by Src2 (Rsrc2) and put the result in register Rdest.

sub Rdest, Rsrc1, Src2		Subtract (with overflow)
subu Rdest, Rsrc1, Src2		Subtract (without overflow)
Put the difference of the integers from register Rsrc1 and Src2 into register Rdest.

xor Rdest, Rsrc1, Src2		XOR
xori Rdest, Rsrc1, Imm		XOR Immediate
Put the logical XOR of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.

7.8 Comparison Instructions

In all instructions below, Src2 can either be a register or an immediate value (integer).

seq Rdest, Rsrc1, Src2		Set Equal†
Set register Rdest to 1 if register Rsrc1 equals Src2 and to be 0 otherwise.

sge Rdest, Rsrc1, Src2		Set Greater Than Equal†
sgeu Rdest, Rsrc1, Src2		Set Greater Than Equal Unsigned†
Set register Rdest to 1 if register Rsrc1 is greater than or equal to Src2 and to 0 otherwise.

sgt Rdest, Rsrc1, Src2		Set Greater Than†
sgtu Rdest, Rsrc1, Src2		Set Greater Than Unsigned†
Set register Rdest to 1 if register Rsrc1 is greater than Src2 and to 0 otherwise.

sle Rdest, Rsrc1, Src2		Set Less Than Equal†
sleu Rdest, Rsrc1, Src2		Set Less Than Equal Unsigned†
Set register Rdest to 1 if register Rsrc1 is less than or equal to Src2 and to 0 otherwise.

slt Rdest, Rsrc1, Src2		Set Less Than
slti Rdest, Rsrc1, Imm		Set Less Than Immediate
sltu Rdest, Rsrc1, Src2		Set Less Than Unsigned
sltiu Rdest, Rsrc1, Imm		Set Less Than Unsigned Immediate
Set register Rdest to 1 if register Rsrc1 is less than Src2 (or Imm) and to 0 otherwise.

sne Rdest, Rsrc1, Src2		Set Not Equal†
Set register Rdest to 1 if register Rsrc1 is not equal to Src2 and to 0 otherwise.

7.9 Branch and Jump Instructions

In all instructions below, Src2 can either be a register or an immediate value (integer). Branch instructions use a signed 16-bit offset field; hence they can jump 215-1 instructions (not bytes) forward or 215 instructions backwards. The jump instruction contains a 26 bit address field.

b label				Branch instruction†
Unconditionally branch to the instruction at the label.

bczt label				Branch Coprocessor z True
bczf label				Branch Coprocessor z False
Conditionally branch to the instruction at the label if coprocessor z's condition flag is true (false).

beq Rsrc1, Src2, label		Branch on Equal
Conditionally branch to the instruction at the label if the contents of register Rsrc1 equals Src2.
beqz Rsource, label		Branch on Equal Zero†
Conditionally branch to the instruction at the label if the contents of Rsource equals 0.

bge Rsrc1, Src2, label		Branch on Greater Than Equal†
bgeu Rsrc1, Src2, label		Branch on GTE Unsigned†
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are greater than or equal to Src2.

bgez Rsource, label		Branch on Greater Than Equal Zero
Conditionally branch to the instruction at the label if the contents of Rsource are greater than or equal to 0.

bgezal Rsource, label		Branch on Greater Than Equal Zero And Link
Conditionally branch to the instruction at the label if the contents of Rsource are greater than or equal to 0. Save the address of the next instruction in register 31.

bgt Rsrc1, Src2, label		Branch on Greater Than†
bgtu Rsrc1, Src2, label		Branch on Greater Than Unsigned†
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are greater than Src2.

bgtz Rsource, label		Branch on Greater Than Zero
Conditionally branch to the instruction at the label if the contents of Rsource are greater than 0.

ble Rsrc1, Src2, label		Branch on Less Than Equal†
bleu Rsrc1, Src2, label		Branch on LTE Unsigned†
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are less than or equal to Src2.

blez Rsource, label		Branch on Less Than Equal Zero
Conditionally branch to the instruction at the label if the contents of Rsource are less than or equal to 0.

bgezal Rsource, label		Branch on Greater Than Equal Zero And Link
bltzal Rsource, label		Branch on Less Than And Link
Conditionally branch to the instruction at the label if the contents of Rsource are greater or equal to 0 or less than 0, respectively. Save the address of the next instruction in register 31.

blt Rsrc1, Src2, label		Branch on Less Than†
bltu Rsrc1, Src2, label		Branch on Less Than Unsigned†
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are less than Src2.

bltz Rsource, label		Branch on Less Than Zero
Conditionally branch to the instruction at the label if the contents of Rsource are less than 0.

bne Rsrc1, Src2, label		Branch on Not Equal
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are not equal to Src2.

bnez Rsource, label		Branch on Not Equal Zero†
Conditionally branch to the instruction at the label if the contents of Rsource are not equal to 0.

j label				Jump
Unconditionally jump to the instruction at the label.

jal labelJump and Link
jalr Rsource				Jump and Link Register
Unconditionally jump to the instruction at the label or whose address is in register Rsource. Save the address of the next instruction in register 31.

jr Rsource				Jump Register
Unconditionally jump to the instruction whose address is in register Rsource.

7.10 Data Movement Instructions

move Rdest, Rsource		Move
Move the contents of Rsource to Rdest.

The multiply and divide unit produces its result in two additional registers, HI and LO. These instructions move values to and from these registers. The multiply, divide, and remainder instructions described above are pseudo instructions that make it appear as if this unit operates on the general registers and detect error conditions such as divide by zero or overflow.

mfhi Rdest				Move From HI
mflo Rdest				Move From LO
Move the contents of the HI (LO) register to register Rdest.

mthi Rdest				Move To HI
mtlo Rdest				Move To LO
Move the contents register Rdest to the HI (LO) register.

Coprocessors have their own register sets. These instructions move values between these registers and the CPU's registers.

mfcz Rdest, Copsource		Move From Coprocessor z
Move the contents of coprocessor z's register Copsource to CPU register Rdest.

mfc1.d Rdest, FRsrc1		Move Double From Coprocessor 1†
Move the contents of floating point registers FRsrc1 and FRsrc1 + 1 to CPU registers Rdest and Rdest + 1.

mtcz Rsource, Copdest		Move To Coprocessor z
Move the contents of CPU register Rsource to coprocessor z's register Copdest.

7.11 Floating Point

The MIPS has a floating point coprocessor (numbered 1) that operates on single precision (32-bit) and double precision (64-bit) floating point numbers. This coprocessor has its own registers, which are numbered $f0--$f31. Because these registers are only 32-bits wide, two of them are required to hold doubles. To simplify matters, floating point operations only use even-numbered registers---including instructions that operate on single floats.

Values are moved in or out of these registers a word (32-bits) at a time by lwc1, swc1, mtc1, and mfc1 instructions described above or by the l.s, l.d, s.s, and s.d pseudo instructions described below. The flag set by floating point comparison operations is read by the CPU with its bc1t and bc1f instructions.

In all instructions below, FRdest, FRsrc1, FRsrc2, and FRSource are floating point registers (e.g., $f2).

abs.d FRdest, FRsource		Floating Point Absolute Value Double
abs.s FRdest, FRsource			Floating Point Absolute Value Single
Compute the absolute value of the floating float double (single) in register FRsource and put it in register FRdest.

add.d FRdest, FRsrc1, FRsrc2	Floating Point Addition Double
add.s FRdest, FRsrc1, FRsrc2		Floating Point Addition Single
Compute the sum of the floating float doubles (singles) in registers FRsrc1 and FRsrc2 and put it in register FRdest.

c.eq.d FRsrc1, FRsrc2		Compare Equal Double
c.eq.s FRsrc1, FRsrc2		Compare Equal Single
Compare the floating point double in register FRsrc1 against the one in FRsrc2 and set the floating point condition flag true if they are equal.

c.le.d FRsrc1, FRsrc2		Compare Less Than Equal Double
c.le.s FRsrc1, FRsrc2		Compare Less Than Equal Single
Compare the floating point double in register FRsrc1 against the one in FRsrc2 and set the floating point condition flag true if the first is less than or equal to the second.

c.lt.d FRsrc1, FRsrc2		Compare Less Than Double
c.lt.s FRsrc1, FRsrc2		Compare Less Than Single
Compare the floating point double in register FRsrc1 against the one in FRsrc2 and set the condition flag true if the first is less than the second.

cvt.d.s FRdest, FRsource		Convert Single to Double
cvt.d.w FRdest, FRsource		Convert Integer to Double
Convert the single precision floating point number or integer in register FRsource to a double precision number and put it in register FRdest.

cvt.s.d FRdest, FRsource	Convert Double to Single
cvt.s.w FRdest, FRsource	Convert Integer to Single
Convert the double precision floating point number or integer in register FRsource to a single precision number and put it in register FRdest.

cvt.w.d FRdest, FRsource	Convert Double to Integer
cvt.w.s FRdest, FRsource	Convert Single to Integer
Convert the double or single precision floating point number in register FRsource to an integer and put it in register FRdest.

div.d FRdest, FRsrc1, FRsrc2	Floating Point Divide Double
div.s FRdest, FRsrc1, FRsrc2	Floating Point Divide Single
Compute the quotient of the floating float doubles (singles) in registers FRsrc1 and FRsrc2 and put it in register FRdest.

l.d FRdest, address		Load Floating Point Double†
l.s FRdest, address		Load Floating Point Single†
Load the floating float double (single) at address into register FRdest.

mov.d FRdest, FRsource		Move Floating Point Double
mov.s FRdest, FRsource		Move Floating Point Single
Move the floating float double (single) from register FRsource to register FRdest.

mul.d FRdest, FRsrc1, FRsrc2	Floating Point Multiply Double
mul.s FRdest, FRsrc1, FRsrc2	Floating Point Multiply Single
Compute the product of the floating float doubles (singles) in registers FRsrc1 and FRsrc2 and put it in register FRdest.

neg.d FRdest, FRsource		Negate Double
neg.s FRdest, FRsource		Negate Single
Negate the floating point double (single) in register FRsource and put it in register FRdest.

s.d FRdest, address		Store Floating Point Double†
s.s FRdest, address		Store Floating Point Single†
Store the floating float double (single) in register FRdest at address.

sub.d FRdest, FRsrc1, FRsrc2	Floating Point Subtract Double
sub.s FRdest, FRsrc1, FRsrc2	Floating Point Subtract Single
Compute the difference of the floating float doubles (singles) in registers FRsrc1 and FRsrc2 and put it in register FRdest.

8 Memory Usage

The organization of memory in MIPS systems is conventional. A program's address space is composed of three parts.

At the bottom of the user address space (0x400000) is the text segment, which holds the instructions for a program.

Above the text segment is the data segment (starting at 0x1000000), which is divided into two parts. The static data portion contains objects whose size and address are known to the compiler and linker. Immediately above these objects is dynamic data. As a program allocates space dynamically (i.e., by malloc, the sbrk system call moves the top of the data segment up.

At the top of the address space (0x7fffffff) is the program stack, which grows down, towards the data segment.

9 Calling Convention

The calling convention described in this section is the one used by gcc, not the native MIPS compiler, which uses a more complex convention that is slightly faster.

A frame consists of the memory between the frame pointer ($fp, which points to the word immediately after the last argument passed on the stack, and the stack pointer ($sp), which points to the first free word on the stack. As typical of Unix systems, the stack grows down from higher memory addresses, so the frame pointer is above stack pointer.

The following steps are necessary to effect a call:

Within the called routine, the following steps are necessary:

Finally, to return from a call, a function places the returned value into $v0 and executes the following steps: